Are you ready to revolutionise the world of wireless communications? Morse Micro is seeking a dynamic and talented Senior Verification Engineer to join our groundbreaking team. If you thrive in a fast-paced, innovative environment and have a passion for pushing the boundaries of wireless technology, this is the perfect opportunity for you!

Your main responsibilities will include:

• Architecting and implementing SystemVerilog and cocotb (Python) testbenches, BFMs and CPU-driven verification flows for a secured Wi-Fi HaLow SoC

• Developing and executing comprehensive SoC verification plans and coverage metrics across SV simulation, Verilator CASIM, assertions, and firmware tests on an embedded RISC-V core; driving verification to closure

• Debugging RTL issues, managing regressions, and leading root cause analysis for failures

• Driving closure of functional coverage targets through AI-assisted verification methodologies, including stimulus generation and intelligent coverage analysis.

• Applying clock domain crossing (CDC) and reset domain crossing (RDC) verification using industry-standard EDA tools to identify and resolve issues

• Verifying security-critical SoC features including secure boot, secure life cycles, OTP programming, and lock enforcement

• Performing gate-level simulation (GLS) with SDF back-annotation to validate post-synthesis timing behaviour

• Running power analysis flows with UPF/CPF RTL simulation

• Implementing and tracking functional and code coverage metrics to assess verification completeness, identify gaps, and drive closure across all testable features and corner cases

• Reviewing design specifications, micro-architecture documents, and interface protocols in collaboration with RTL design engineers; translating requirements into comprehensive verification test plans and identifying risk areas early in the design cycle

Essential skills and experience:

• Proven expertise of more than 5 years in at least one of the pre-silicon ASIC verification methodologies such as System Verilog, UVM or Formal

• Proficiency in SystemVerilog testbench development, including writing BFMs for standard bus protocols such as AMBA and TileLink

• Practical expertise in COCOTB for developing Python coroutine testbenches and embedding software reference models.

• Strong C programming skills for embedded firmware-level verification

• Experience with security IP verification concepts

• Working knowledge of gate-level simulation and SDF back-annotation for post-synthesis sign-off

• Solid understanding of CPU, memory, cache, DMA, and on-chip interconnect verification

• Experience with bootloader and bare-metal firmware drivers is a plus

• Experience with formal verification is a plus

What we offer:

• Competitive salary and stock option package

• 10 days work remote from anywhere in the world

• Opportunity to work at a cutting-edge startup company

• Chance to make a significant impact on the future of wireless technology

• Collaborative and supportive work environment

Who we are:

Morse Micro is Australia’s largest semiconductor company building Wi-Fi HaLow (802.11ah) chips for the Internet of Things (IoT). We are a team of wireless experts that love to work hard, innovate & invent. Together, we are building the world’s lowest power Wi-Fi technology that will enable billions of IoT devices to connect securely to the internet. We are a global team with offices in Sydney & Picton (Australia), Irvine & Bay Area (USA), Bangalore (India), Cambridge (UK), Hangzhou & Shenzhen (China) and Taipei (Taiwan).

How to apply:

If you are interested in building the first 802.11ah chipset together with the inventors of Wi-Fi, then send us your resume and application letter and tell us why you should become Morse Micro's next Senior Verification Engineer.