Where can I find Atria Logic interview experiences by job title?

Verification Engineer (8) ; Design Engineer (2) ; FPGA Design Engineer (2) ; Intern (2)

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Atria Logic

Atria Logic interview questions

Updated 3 Dec 2024

based on 13 ratings

Difficulty

Average

Experience

Very positive

How others got an interview

58%
Applied online
Applied online
17%
Other
Other
17%
Recruitment agency
Recruitment agency
8%
Campus recruiting
Campus recruiting

Interview search

13 interviews

Design Verification Engineer Interview

3 Dec 2024

Anonymous interview candidate

No offer

Positive experience

Difficult interview

Application

I applied through university. The process took 6 days. I interviewed at Atria Logic (Tirupati) in Aug 2024

Interview

Good and covered all the topics form the dv All the concepts from digital verilog system verilog UVM and projects and protocols related questions . Over all experience was good enough I tried my level best there

Interview questions [1]

Question 1

All concepts related digital verilog sv UVM

Answer question

Design Verification Engineer Interview

9 Sept 2024

Anonymous interview candidate

No offer

Positive experience

Average interview

Application

I applied through other source. I interviewed at Atria Logic (Tirupati)

Interview

Three rounds, 2 technical and one hr round , everything is one to one round, and you should be well prepared to crack this ,you will get very good experience after completion of this process.

Interview questions [1]

Question 1

Can you just Introduce yourself

Answer question

Verification Engineer Interview

28 Jan 2021

Anonymous interview candidate

Declined offer

Neutral experience

Difficult interview

Application

I applied online. The process took 1 week. I interviewed at Atria Logic

Interview

Basically there were three rounds: 1) Written test(SV and UVM basically) 2) Technical interview (They asked me deep questions on SV and UVM) 3) HR round(This round was to check your soft skills)

Interview questions [1]

Question 1

Difference between logic and reg? Difference between static casting and dynamic casting? resouce db and its significance? What is throughput rate? event scheduler in SV? UVM objections? Driver sequence handshake?

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Viewing 1 - 5 of 13 Interviews

Jobs at Atria Logic

Senior Verification Engineer

Sunnyvale, CA

USD 132K - USD 178K /yr

(Glassdoor Est.)

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