I applied through other source. I interviewed at Cadence Design Systems (Hyderābād) in June 2021
Interview
I had an interview for design Verification:
1st round :
Self introduction
Basic questions from digital electronics
Verilog
C programming
2nd around:
Questions and code related to
Verilog FSM code
Various clock divider circuits implemention
SystemVerilog topics like
polymorphism
abstraction
interface
clocking block
arrays
Questions and code :
SystemVerilog functional coverage and assertions
Questions related to protocols which I was mentioned in my resume.
Questions related various UVM topics.
Some logical questions
Interview questions [1]
Question 1
What is the difference between Moore and melay circuits?
Implement and write a code to detect 10110 Sequence?
Frequency divide by 7
UVM phrases
What is inheritence, ploymorphism, and abstraction in SystemVerilog?
I interviewed at Cadence Design Systems (Bengaluru)
Interview
It was on campus placement. Resume shortlisting was done and then direct interview was scheduled(no written test). Two rounds of interview an hour each. Both the rounds were technical and mostly focused on systemverilog and verification.
I applied through university. I interviewed at Cadence Design Systems (Bengaluru)
Interview
It was a technical interview, duration was around 50 min, recruiter asked many questions starting from fundamentals. Asked about projects in depth. Overall experience was great but i couldn't clear the interview. Questions were easy to moderate level. Asked few coding related questions as well!!
interviewers were friendly and supportive. the questions were moderate to hard. aptitude was easy to solve. overall it went good and was a very good exp for me so far
Interview questions [1]
Question 1
1. on bits and bytes
2. virtual class output questions were there
3.
