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      MathWorks

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      MathWorks interviewsMathWorks FPGA TARGETS and SPC HDL INTERN interviewsMathWorks interview


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      FPGA TARGETS and SPC HDL INTERN Interview

      18 Jan 2014
      Anonymous interview candidate
      Boston, MA
      No offer
      Positive experience
      Average interview

      Application

      I applied through an employee referral. The process took 8 weeks. I interviewed at MathWorks (Boston, MA) in Nov 2013

      Interview

      I got a email from HR to schedule for technical interview.Interview took for 1 and half hour.Interview was quite simple .interview was very positive .. interview was particularly on FPGA/ASIC ..Verilog ,Vhdl..He got satisfied with my performance .. he gave an assignment type ..to code the design two tap fir filter in matlab and vhdl ,he asked me to send those simulation files through email. I got an email from an another person for scheduling the second telephonic interview .. this phone interview I troubled to answer for the most of the questions... though questions were from my resume itself ..he went a bit deep in questioning... still I felt there are chances of getting selected .. till now I haven't heard anything from mahworks .. I emailed HR twice about my result .. same answer both of the times .. we currently taking time to interview the other candidates will get back to you soon..its been 1 and half month since i had an interview ..i didnt hear anything from those guys ...still waiting to hear something but... they changed position title now to Software intern and spc hdl

      Interview questions [1]

      Question 1

      question were quite simple in first interview .. very things basics ..he didn't go much into deep ..in the second interview c-programming pointers , void statement and diff b/w static memory location and dynamic memory location matlab- diff script file and function file.. call by reference ,pass by reference.. a.b and a*b verilog initial statement and fork and join , fpga chipscope,pci interface ,,simulators modelsim ..nc verilog,
      Answer question
      1