One 5.5 hour interview.
Extensive and thorough
Slightly repetitive due to meeting with several members of the team
However never felt to drag on despite the length
All members were understanding and offered advice along the way
Interview questions [1]
Question 1
To draw the schematic of several basic gates using pmos and most transistors
I applied through university. The process took 5 days. I interviewed at Microchip Technology (Bengaluru) in Nov 2022
Interview
On-campus FTE interview. Lasted for 45 mins. My experience with the first two interviewers was great. The third interviewer started by asking analog questions which I said I was not comfortable with. He said, alright - I'll ask digital questions. After I answered his digital questions, he reverted to asking analog questions.
Interview questions [1]
Question 1
1st two interviewers : Volatile v/s Non Volatile memory (RAM/ROM) Basic Verilog questions like blocking v/s non-blocking, continuous vs procedural etc Explanation of all my FPGA/Verilog-related projects 2:1 MUX using basic gates Setup vs Hold, which is more important, why is it caused. metastability - how to fix it FIFO uses ASIC design flow How does synthesis happen Synchronisation vs Asynchronous clock 3rd Interviewer: Equation for power in a resistor Analysis of parallel LC circuit 2 i/p AND gate where each input is getting pwm of period 10. But on input B, an inverter of 1ms delay is attached. What's the resulting waveform? Is it practical to be used with a f/f Transfer characteristic of NOT gate Can NOT gate be used as an amplifier
I applied online. The process took 1 day. I interviewed at Microchip Technology in Mar 2020
Interview
It was a telephonic interview. They called on the exact time as scheduled. The interviewer made me comfortable by describing the role and job location. The interview was tricky and in-depth questions were asked on basics. They gave feedback on the same day. Unfortunately I did not perform well.
Interview questions [1]
Question 1
Difference between the latch and flip flop, where is latch used, Should it be used, how will you prove that the fabricated chip has setup time issues, temperature effect on setup time hold time and clock