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      onsemi

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      Design Engineer Interview

      11 Oct 2022
      Anonymous interview candidate
      No offer
      Positive experience
      Average interview

      Application

      I interviewed at onsemi

      Interview

      First accademic based test in which arround 33 questions of ECE subject. Second is technical round where mostly ask c or c++ related questions. And third is HR round here simply introduction to eachother.

      Interview questions [1]

      Question 1

      Why do you want to join this company?
      Answer question

      Other Design Engineer interview reviews for onsemi

      Design Engineer Interview

      13 June 2023
      Anonymous interview candidate
      Portland, OR
      No offer
      Negative experience
      Difficult interview

      Application

      I interviewed at onsemi (Portland, OR)

      Interview

      I was referred by a current employee. First one telephone interview and then a on site interview, The Phone interview was pretty easy guy the on-site was very difficult. For the lunch they took me to a Chinese restaurant which wasn't the best option because non of us were Chinese.

      Interview questions [1]

      Question 1

      SVA, state machines, some c programs
      Answer question

      Design Engineer Interview

      9 Sept 2020
      Anonymous employee
      Bengaluru
      Accepted offer
      Positive experience
      Easy interview

      Application

      I applied online. The process took 2 weeks. I interviewed at onsemi (Bengaluru) in Aug 2020

      Interview

      The process took almost 2 weeks. Initially one telephonic round and then a video call interview which took 4 hours. Four persons interviewed with each one hour. The questions were mainly to check your digital design ability.

      Interview questions [6]

      Question 1

      1. Normal mux and priority mux design
      Answer question

      Question 2

      2. Latch and flop design using mux
      Answer question

      Question 3

      3. CDC and synchronization techniques
      Answer question

      Question 4

      4. Flop design which should sample data on both edges
      Answer question

      Question 5

      5. Minimum asynchronous FIFO depth
      Answer question

      Question 6

      6. pulse synchronization(fast to slow clock & slow to fast) which one is difficult
      Answer question

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