Consumtions with and without pipeline, how to test ASICs, how would you get to know if a number is a power of 2.
Rtl Design Engineer Interview Questions
212 rtl design engineer interview questions shared by candidates
There are 5 holes in a line, and there is a rat in one of it. Each turn the rat will move either left or right, but never stay in the same hole, and each turn you can check one hole. The holes are in a line so when the rat reach one end, it must move back in the next turn. What is your strategy to catch that rat?
Lot of question on Power like different types of Power consumption in circuits? What is clock gating? Explain types of techniques to reduce static power at RTL level
write a verilog code for sequence detector fsm 1001
How to detect power of "2" in a given binary number sequence with minimum hardware? For example detect "0001", "0010", "0100", "1000" etc. in incoming series.
RTL design , verilog, system verilog?
Name main stages of SystemVerilog simulator.
Mainly focused on set-up and hold time
Introduction about me in brief words
They asked questions based on timing , skew, jitter and Digital Desgin. A Few questions based on relevant information in the your resume and other basic questions like such. Some python Data structure basics.
Viewing 1 - 10 interview questions