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      ASIC Design Engineer Interview

      9 May 2018
      Anonymous interview candidate
      No offer
      Positive experience
      Average interview

      Application

      I applied online. The process took 7 weeks. I interviewed at Google

      Interview

      Very Methodical and recruiters were very helpful all along. Interviewers were looking for good overall understanding versus just high level. Hardcore technical interview and no behavioral questions were asked.

      Interview questions [1]

      Question 1

      FSM Design
      Answer question
      13

      Other ASIC Design Engineer interview reviews for Google

      ASIC Design Engineer Interview

      9 Aug 2018
      Anonymous interview candidate
      Declined offer
      Positive experience
      Average interview

      Application

      I applied through an employee referral. The process took 2 months. I interviewed at Google in July 2018

      Interview

      Referred by a friend and got a call from the recruiter a few days later. Had a phone interview and later was called upon for an onsite interview. Was asked to code digital logic in verilog in a shared google doc

      Interview questions [4]

      Question 1

      Implement a Hardware based LRU scheme for a 4-way set associative cache.
      Answer question

      Question 2

      Based on the critical, find the max frequency of operation (based on the combi, flop delays, flop setup and clock skew).
      Answer question

      Question 3

      Detect that N numbers have arrived based on a control signal. Flag the average of all the N numbers once the N-numbers have arrived.
      Answer question

      Question 4

      Async FIFO sizing. Thru put of putting every clock cycle. Both read and write clocks are same speed
      Answer question
      34