Career fair in Oct. Got a call for phone interview in november. It lasted for 1 hour 10 mins. All questions were asked to judge the superficial knowledge. Some of the vital questions I remember were: 1. What are you interested in? preference? Ans: Physical design, RTL and (not truly) verification 2. What is physical design from your perspective? 3. Why do we size digital logic gates? What is it's significance? 4. Consider a situation wherein the sizing of all gates is changed from 2:1 to 1.5:1. WHAT would be the reason to change? 5. What is noise margin? How do you change it? 6. What is setup and hold time? How to fix setup and hold time violation during circuit design and after tape out? I had to explain this lot in detail. Many intermediate questions were asked. 7. What is AOI22 gate circuit? Draw it at transistor level and tell me the pull down network structure. 8. What are the sources of leakage in a MOS transistor? Explain each of them. Question on subthreshold current, gate tunneling, hot electron effect, reverse leakage current. 9. What is electromigration? How to fix the problem? 10. How is logical effort useful? What is logical effort of a 2 input NAND. NOR gate? Connect them in chain and tell the logical effort of path. Do we need to specify load to determine LE of path? 11. If wire of length, L, has delay, D, what is the delay of wire of length 2L? (I used Elmore delay and explained him how I reached conclusion. During the process I constantly mentioned Elmore delay as "Euler delay"!! we had a good laugh at my folly) 12. Why do we need cache? what is the need of L1 L2 and L3 cache? what is direct , fully associative and set associative mapping? If a direct mapped cache of cache line L has miss rate M, and another cache having set associativity as 2 has same miss rate, determine the cache lines. 13. What is the need of pipelining? Advantages and disadvantages. How many stage pipeline did you study? Did you use registers or latches to pipeline? Difference between latch and register. 14. Mention the power dissipation ways in a CMOS gate. How do you reduce it? Finally he explained me the vastness of physical design domain and told me that ASIC design knowledge is required to go for it. Also spoke about the relevant work in industry. It was a very good discussion. I could answer most of the questions satisfactorily. I did not let go any of the questions unanswered as I had nearly everything covered in my course work. On Dec 5, I received an email inviting me for an site interview and had an option to choose all or among the 3 teams. The site interview were quite long and dealt with every concept of VLSI. Some of the vital topics dealt were: 1. Basic CMOS gates sizing. The basics behind that. Explain using some example gates. 2. Draw the schematic of a circuit described in VHDL. Determine the critical path. What would you do to speed it up? Change some of the static gates in circuit with dynamic logic gates and see the difference in logical effort it brings. (This was the best discussion I had. I felt very confident after this!!) 3. Draw the graph of charging and discharging current in an inverter versus Vds. 4. Implement 2:1 MUX using Transmission gates and static logic? What are their pros and cons? Which one would you use to implement 8:1 MUX? Why? 5. Implement a 7:1 MUX with input signals arriving at different times. 6. What is EM, IR drop, noise margin, hot carrier effect, gate tunneling, subthreshold conduction and every thing related to layouts and basics of CMOS gate 7. Explain the projects in resume? If you get a chance to work on any other block again, which one would you choose and why? Critical path determination in project circuit. 8. Steps from RTL description of circuit to tape out? Speak about each of them in detail. 9. DFT and scan chain. They provided an example and asked to find the fault in the circuit. 10. Questions based on STA, Prime Time tool. 11. Questions on synthesis in FPGA kit The interviews were long and based on details and basics. It was a very good experience. They never overwhelmed me with procedures and kept everything simple. The whole on site interview process lasted for 6 days. The very next day after final interview rose with the good news. I made it to all the 3 teams and now I had to choose the team whom I shall work with. Most of the decisions were taken and tentative dates finalised (!!) within a day. It was indeed a wonderful journey.